Multi-Core Architecture — Cache Coherence

Why Multiple Cores?

The Power Wall (~2005)

Frequency scaling stopped: power grows with f·V², and heat became unmanageable past ~4 GHz. So we stopped scaling up and started scaling out — more cores at the same clock.

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Cache Topology

Private vs Shared

Each core owns a private L1-I + L1-D (~1 ns) and a private L2 (~4 ns). All four cores share one L3 / LLC (~35 ns) and one memory controller.

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The New Problem

MESI Protocol

Four private copies of the same line must agree. Every line is Modified, Exclusive, Shared or Invalid — and the hardware enforces one writer at a time.

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The New Bug Class

False Sharing

Coherence works on whole 64-byte lines, not variables. Two independent variables on one line cause invalidation ping-pong and can cost ~10× throughput.

▪ Quad-Core Die · Private L1/L2 · Shared L3

4-core die · 16 MB LLC

⇄ On-Chip Ring Bus / Interconnect

Snoop · coherence messages · ~10 ns core-to-core

Shared L3 Cache (LLC)

Last Level Cache

16 MB · ~35 ns · shared by all cores · coherence directory lives here

Integrated Memory Controller · ~2 channels

— package edge · off-die —

Main Memory

DRAM

32 GB · ~80 ns · 64-byte cache lines

Coherence Trace

Cache Line State per Core

Address	Core 0	Core 1	Core 2	Core 3	Value

MESI State Machine

lit arrow = this step’s transition

MESI Legend

Modified — only this core has it, and it is dirty; memory is stale.

Exclusive — only this core has it, and it is clean; a write needs no bus traffic.

Shared — several cores hold a clean copy; reads are free, writes must invalidate.

Invalid — no usable copy here; the next access is a miss.

Pick a scenario above and press Play. Each core's L1-D and L2 badges track the MESI state of the line being traced.

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