Moore's Law & The Power Wall

Moore's Law (1965)

Transistors double every ~2 years

Gordon Moore observed transistor counts doubling roughly every two years. It held for half a century — an exponential ride from 2,300 to 100+ billion transistors.

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Dennard Scaling (1974)

Smaller also meant cooler

Smaller transistors also used less power, so chips could clock faster for free. This is the part that BROKE around 2006.

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The Power Wall

P ≈ C · V² · f

Voltage stopped shrinking, so higher frequency meant quadratically more heat per mm². Power density approached that of a rocket nozzle.

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The Fix: Go Wide

More cores, moderate clocks

Instead of one faster core, spend the transistors on MORE cores at moderate clocks. Multi-core (Part 5) was born of thermodynamics, not preference.

Two curves, one divergence — 1970 → 2025

Hover any dot for chip details · use the scrubber below to walk the story

Transistor count (violet)

Clock speed in Hz (amber)

Power-wall era (post-2004)

Multi-core era begins (2005)

Shared log axis · both series are orders of magnitude on a growth story

Timeline scrubber — era by era

Transistors

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select an era

Clock speed

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select an era

Since 1971

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growth multiples

Era 0 / 8

Read the two curves against each other. Up to 2004 they rise in lockstep — more transistors and more megahertz, every generation. After 2004 the violet line keeps its slope for another twenty years while the amber line goes flat. That gap is the power wall, and everything the industry built after it — multi-core, SIMD, GPUs, accelerators — exists to convert the transistors we still get into performance we can no longer buy with frequency.

← → arrow keys also step through the eras.

Narrative log

The heat panel — power density, on a log ladder

Watts per square centimetre of surface

Patrick Gelsinger's 2001 warning: on the old trend, chips would have reached the power density of a rocket nozzle by ~2010. They didn't — because we stopped raising frequency.

Dynamic switching power

P ≈ C · V² · f

C switched capacitance — how much silicon flips

V supply voltage — squared

f clock frequency

1 Until ~2004, V fell with every node. Dennard scaling shrank the transistor and dropped the voltage, so V² collapsed fast enough to pay for a higher f. Speed was effectively free.
2 Then voltage hit a floor: leakage current. Below roughly 1 V the gate can no longer fully switch off — sub-threshold and gate-oxide leakage burn power even when the transistor is idle. Lower V also means slower switching, so you cannot simply take both.
3 With V pinned, f became the only knob — and it was maxed. Power now rose linearly with frequency on a die that was getting smaller, so power density exploded. At ~100 W in a ~100 mm² die you are already at the practical limit of an air cooler. The knob was turned all the way.

Still exponential

Transistors

Moore's Law kept delivering — roughly 2× every two years, into the hundreds of billions.

Broken since ~2006

Dennard scaling

Voltage stopped falling, so the free frequency ride ended for good.

The only way out

Spend it on width

More cores, wider vectors, on-die accelerators — performance per watt, not per hertz.

Every architectural idea in the rest of this series — multi-core, cache coherence, SIMD, GPUs, kernel-bypass networking — is downstream of this one thermodynamic fact.

The consequence — one fast core vs. many moderate cores

Same transistor budget, two very different thermal outcomes

Hypothetical 10 GHz core

Push one core to 10 GHz and P ≈ C·V²·f lands you near 1,000 W on a die the size of a stamp. No air cooler, no heat pipe, no consumer water loop moves that much heat off ~2 cm² of silicon. It is physically uncoolable.

DEAD END · NEVER SHIPPED

4 × 3 GHz cores

Four cores at a moderate clock sit at roughly 100 W — an ordinary heatsink handles it. Total throughput is far higher than the 10 GHz fantasy, and it actually ships — if software can use them.

SHIPPED 2005 · STILL HOW IT WORKS

The catch: the speedup is limited by the serial fraction of the program — Amdahl's Law — and the cores must agree about memory. That's Part 5.