Computer Architecture Dashboard

Abstract Model (1936)

Turing Machine

Infinite tape, read/write head, state table. Proves any computation is a sequence of simple symbol operations.

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Hardware Model (1945)

Von Neumann Architecture

CPU + Memory + I/O sharing a single bus. Instructions and data live in the same address space.

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The Bottleneck

Memory Wall

CPU gets faster every year; DRAM access stays slow (~60–100 ns). Cache hierarchy bridges the gap.

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Solution

Cache Hierarchy

L1→L2→L3→RAM→Storage. Keep hot data close to the CPU. A cache hit costs 1 ns; a RAM miss costs 60×.

▪ CPU Core (Single)

Registers

~32 × 64-bit · 0.3 ns

Control Unit

Fetch · Decode

ALU · FPU · Branch

Execute · Write Back

L1 Cache

L1-I + L1-D

Size32–64 KB

Latency~1–4 ns

Bandwidth~1 TB/s

L2 Cache

Unified

Size256 KB–4 MB

Latency~4–12 ns

Bandwidth~400 GB/s

L3 Cache (LLC)

Last Level Cache

Size8–64 MB

Latency~30–40 ns

Bandwidth~100 GB/s

Main Memory

DRAM / RAM

Size8–256 GB

Latency~60–100 ns

Bandwidth~50 GB/s

Secondary Storage

NVMe SSD / HDD

Size256 GB–20 TB

Latency~100 µs–10 ms

Bandwidth~7 GB/s

⇓FETCH

Load instruction

☰DECODE

Parse opcode

⚡EXECUTE

ALU / memory op

↑WRITE BACK

Store result

Simulation Log

Memory Hierarchy State

CPU Registers

—

L1 Cache

empty

L2 Cache

empty

L3 Cache

empty

RAM

0x1A4F → 42

Storage

program on disk

Elapsed Time

0 ns

Waiting to start

Step 0 / 0

Intuition Pump

If a clock cycle were one second

Nanoseconds are unimaginable, so stretch them. A 4 GHz core retires one cycle every 0.25 ns — call that 1 second of human time. Every latency in the hierarchy then becomes something you can actually feel waiting for.

1 CPU clock cycle

1 second

real: 0.25 ns @ 4 GHz

L1 cache hit

4 seconds

real: ~1 ns

L2 cache hit

16 seconds

real: ~4 ns

L3 cache hit

2 minutes

real: ~30 ns

DRAM access

5 minutes

real: ~75 ns

NVMe SSD read

11 hours

real: ~10 µs

HDD seek

5 months

real: ~4 ms

Network SF→NY

8 years

real: ~60 ms RTT

Figures are approximate and rounded for intuition — real latencies vary by microarchitecture, clock speed, DRAM timings, queue depth and route. The bars are on a logarithmic scale; on a linear one the first five tiles would be invisible. That gap is exactly why caches exist: a single trip to DRAM costs the core roughly 300 cycles of "waiting around," and a network round-trip costs a quarter of a billion.