The 1945 blueprint: one memory for both program and data
• EDVAC 1945
• Stored Program
The Document
The EDVAC Report (1945)
John von Neumann's “First Draft of a Report on the EDVAC” described the
stored-program computer: the design every laptop, phone, and server still follows.
›
The Breakthrough
The Big Idea: Stored Program
Instructions are just numbers in the same memory as data. A program can be loaded,
changed, even written by another program — software becomes possible.
›
The Blueprint
Five Parts
Control Unit, ALU, Memory, Input, Output — connected by a shared bus.
›
The Cost
The Von Neumann Bottleneck
One bus means the CPU fetches EITHER an instruction OR data each cycle, never both.
This bottleneck is why the cache hierarchy (Part 3) exists.
Address on bus
Instruction on bus
Data on bus
Instruction cell
Data cell
Unused
Program: C = A + B — 3 instructions, 7 bus crossings
The Five Parts · One Shared Bus
Input
Keyboard · loads the program
Output
Screen · shows the result
Central Processing Unit
idle
Control Unit
Fetch · decode · sequence
PC
00
IR
—
ALU
Add · compare
ACC
—
0
Bus crossings
SHARED BUS
ADDR + DATA
On the bus
idle
Memory — 16 addressable words
one address space
00–05 program (instructions)
10–12 data (A, B, C)
Same memory, both kinds. Nothing in the hardware marks cell 00 as “an instruction” and
cell 10 as “a number” — only the PC decides what gets executed. That is the stored-program idea,
and also why a bad jump can execute your data.
⇓Fetch
PC → bus → IR
☰Decode
opcode + operand
⚡Execute
ALU / memory / PC+1
Bus crossings
0
Every instruction and every operand travels the same wires.
PC
program counter
00
IR
instr. register
—
ACC
accumulator
—
■ HALTED
Instruction Cycle Log
Program & Data
As stored in memory
00LOAD 10; ACC ← MEM[10]
01ADD 11; ACC += MEM[11]
02STORE 12; MEM[12] ← ACC
03HALT;
107; A
115; B
120; C = result
Why not two memories?
You could give the machine separate instruction and data memories, each with its own bus —
that is the Harvard architecture, and it lets the CPU fetch an instruction and an operand in the
same cycle instead of taking turns. Von Neumann chose one memory because it is far simpler and
because a single address space is what makes programs editable data: compilers, loaders, and operating
systems all depend on it.
Modern chips quietly take both deals. The programmer still sees one von Neumann address space, but
inside the CPU the L1 cache is split into L1-I (instructions) and L1-D (data) — a Harvard
split at the top of the hierarchy, so a fetch and a load no longer collide. That is exactly where
Part 3 picks up.
Von Neumann — one bus
Instruction OR data per cycle. Simple, flexible, self-modifying. Bus is the bottleneck.
Harvard — two buses
Instruction AND data per cycle. Faster, but rigid. Survives today as L1-I vs L1-D and in DSPs/microcontrollers.